The present invention relate to a pulse generator circuit, particularly for non-volatile memories.
More particularly, the invention relates to a circuit for generating mutually correlated pulses which are suitable to stimulate a plurality of internal units in a non-volatile memory.
Generally, the cells of a conventional non-volatile memory are organized in a single array, and in the normal operating mode they are read by pointing to the external address that directly points to one of the cells of the memory array.
This kind of memory organization does not require particular synchronization activities internally.
However, when additional circuits, such as a counter in order to perform a plurality of sequential read operations, are introduced in order to improve the memory and provide faster operation thereof, a problem arises in synchronizing the propagation of a normal memory read stream and the occurrence of an address change, which can be triggered both internally (in the case of an increment of the counter of the memory) and externally (pointing to a random location, as occurs in the execution of a "skip" operation).
In addition to updating the new reading path, there can be other internal activities, such as preventative measures against the effects of buffer transitions (i.e., against the noise that can be generated) and feedback to the timing circuit of the memory in order to determine the end of pulses to be implemented.
In some embodiments, such as for example the memories organized in the so-called interleaved mode, the memory cells are arranged in two separate memory banks, each with its own counter.
In this last type of memory there is also another problem which is due to the fact of having to decide which of the two counters of the two banks is to be incremented, when to begin the increment, and also perform any suspension of the increment updates.
It is therefore evident that it is necessary to synchronize the various parts of the memory.
Moreover, in order to achieve the best possible performance, some of these synchronization pulses must have minimal duty cycle characteristics.
Although the duty cycle must be minimal, it must nonetheless ensure the correct generation of the pulse and its correct use.
The pulse generator circuits currently used in memories do not perform this function of generating pulses of minimal duration with the assurance of full functionality and therefore they are not suitable when one wishes to obtain high performance from a memory.